One of the critical performance parameters of a very large scale integrated (VLSI) circuit is the propagation delay through the device. VLSI devices include hundreds or thousands of transistors and are conventionally used in high speed digital computer systems. Variations in propagation delay through signal paths of the device affect the overall operating speed of the computer. Unusually long propagation delays are indicative of a malfunction in the VLSI device. Accordingly, it is a common practice to measure propagation delays through selected signal paths of VLSI devices before they are incorporated into a computer or other digital system.
As used herein, propagation delay refers to the time required for an input signal to propagate from the input of the prescribed circuit path to the output of that circuit path. The propagation delay is measured by measuring the time difference between the input and output signals.
A well-known principle of test measurement is that the measurement error should be much less than the expected value of the parameter being measured. For example, in measuring a 100 nanosecond propagation delay, a tester error of .+-.1 nanosecond is sufficient to obtain .+-.1% measurement accuracy. However, when testing state-of-the-art high speed digital circuits, it is not feasible to follow this principle since tester errors are often comparable to the parameter being measured. A test instrument having an accuracy of .+-.1 nanosecond provides a meaningless measurement when the propagation delay being measured is one or a few nanoseconds since the measured value can be in error by up to 100%. Test instruments with the required level of accuracy are not available at present. Clearly, another approach to measuring short propagation delays is necessary.
In the past, the above-noted problem has been overcome by adding circuits in order to increase the measured propagation delay. For example, gates may be added outside the functional circuit path to increase the measured propagation delay from 1 to 10 nanoseconds. However, such added gates are nonfunctional and add substantially to the total chip area. Furthermore, added gate circuitry may not be in the same area of the chip and may be constructed of different materials, thereby introducing uncertainties into the measured propagation delay.
Another problem in the measurement of propagation delay through digital circuits is that the circuits frequently contain clocked- circuit elements between input and output pins. When this occurs, it is impossible to measure propagation delay.
It is a general object of the present invention to provide improved methods and apparatus for measuring the dynamic characteristics of VLSI devices.
It is a further object of the present invention to provide methods and apparatus for measuring the propagation delay of VLSI devices without adding substantial circuitry to the VLSI device.
It is yet another object of the present invention to provide methods and apparatus for accurately measuring the propagation delay through very high speed digital VLSI devices.
It is still another object of the present invention to provide methods and apparatus for measuring the propagation delay of VLSI devices including one or more clocked circuit elements in operational circuit paths between input and output pins.